Senior Hardware Design Engineer

 

Description:

Teresol Pvt. Ltd. (Pvt.) Ltd. is seeking an experienced Senior Hardware Design Engineer – FPGA to join its Hardware Engineering team. The role involves leading FPGA design and development, contributing to complex hardware systems, and mentoring junior engineers while working on AMD Zynq-based platforms.

 

Key Responsibilities:

• Design, develop, review, and optimize RTL implementations using VHDL, Verilog, and SystemVerilog for AMD Zynq FPGA platforms.

• Develop and maintain simulation testbenches to ensure functional correctness and design coverage.

• Perform functional and timing simulations and resolve timing closure challenges.

• Port and migrate RTL designs across different FPGA device families.

• Lead hardware bring-up, debugging, and validation using laboratory equipment.

• Prepare comprehensive technical documentation including architecture diagrams, simulation reports, and optimization analysis.

• Collaborate closely with software, system, and hardware engineering teams throughout the development lifecycle.

• Drive timing closure and optimize resource utilization for complex multi-clock FPGA designs.

• Review RTL and verification deliverables developed by junior engineers.

• Lead IP integration activities using Vivado IP Integrator (IPI).

 

Technical Requirements:

Core FPGA & Digital Design Expertise:

• Hands-on experience with AMD Zynq-7000 or Zynq UltraScale+ SoC/MPSoC platforms.

• Strong proficiency in RTL design using Verilog, VHDL, and/or SystemVerilog.

• Strong understanding of digital design fundamentals, including FSMs, pipelining, and clock domain crossing (CDC).

• Experience in simulation and verification methodologies; familiarity with UVM is an advantage.

• Strong knowledge of timing analysis, setup/hold constraints, and timing closure techniques.

• Proven experience achieving timing closure in complex FPGA designs.

• Experience with AMD/Xilinx IP cores such as AXI Interconnect, DMA, MIG, and FIFO.

• Strong understanding of Zynq PS–PL architecture and AXI4-based protocols (AXI4 / AXI4-Lite / AXI4-Stream).

• Experience integrating custom RTL IP into Vivado block designs.

• Working knowledge of Vitis and PetaLinux for embedded software/firmware co-development.

• Experience with advanced Vivado features including hierarchical design, partial reconfiguration, and debugging tools (ILA/VIO).

 

Additional Competencies:

• Proficiency in Git and modern collaborative development workflows.

• Strong technical writing and communication skills.

• Ability to independently manage priorities and meet project deadlines.

• Experience in mentoring and guiding junior engineering staff.

 

Education:

Bachelor’s / Master’s degree (B.Sc. / B.E. / M.Sc. / M.E.) in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline is required.