Description:
DreamBig Semiconductor is hiring a highly skilled Physical Design Engineer to join our team in Karachi. This role requires hands-on expertise in RTL to GDS, synthesis, floorplanning, placement & routing, and static timing analysis (STA). The ideal candidate should have experience working with TSMC process technologies and GDS generation & signoff.
Key Responsibilities
- Execute end-to-end physical design tasks, including placement, timing optimization, clock tree synthesis (CTS), and routing.
- Perform synthesis, chip/block-level floorplanning, and pin assignments.
- Conduct pre-layout STA to ensure timing feasibility and constraint validation.
- Review clock specifications at the block and top levels to ensure design completeness.
- Perform signoff tasks, including RC extraction, STA, IR drop analysis, and physical verification.
- Lead PPA (Power, Performance, Area) optimization efforts to meet aggressive project timelines.
- Collaborate with ASIC and design teams to ensure seamless integration.
Key Skills & Expertise (Mandatory)
- Physical Design (RTL to GDS)
- Synthesis, Floorplanning, Placement & Routing
- Static Timing Analysis (STA)
- TSMC process technologies
- GDS generation & signoff
Requirements
- Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.
- 2-5+ years of experience in ASIC physical design.
- Strong knowledge of digital tapeout processes and advanced nodes.
- Hands-on experience with industry-standard EDA tools (Cadence, Synopsys, etc.).
- Expertise in IR drop analysis, physical verification, and debugging layout issues.
- Proficiency in Verilog HDL, scripting (Perl/Tcl/Python), and physical design libraries.
- Strong problem-solving and analytical skills.
- Excellent communication and teamwork abilities.